whitequark
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0ef5ced492
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compat.sim: match clock period.
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2018-12-14 16:39:52 +00:00 |
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whitequark
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17d26c8329
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compat: add run_simulation shim.
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2018-12-14 16:22:18 +00:00 |
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whitequark
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88970ee29f
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pysim.back: fix add_sync_process wrapper to handle signals correctly.
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2018-12-14 16:21:53 +00:00 |
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whitequark
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3bc3647380
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compat.fhdl.module: fix specials.
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2018-12-14 16:14:08 +00:00 |
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whitequark
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3b23645fb7
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compat: add fhdl.specials.TSTriple shim.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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7200346249
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genlib.io: import TSTriple from Migen.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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50ba443f92
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fhdl.ast: fix Switch with constant test.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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a0d555a9fc
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compat: add genlib.cdc.MultiReg shim.
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2018-12-14 16:01:38 +00:00 |
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whitequark
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baba47251c
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compat.fhdl.module: update deprecation messages.
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2018-12-14 16:01:38 +00:00 |
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whitequark
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9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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whitequark
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e3f32a1faf
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back.pysim: better naming. NFC.
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2018-12-14 15:21:13 +00:00 |
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whitequark
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68f8dabb29
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Travis: install pyvcd.
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2018-12-14 14:47:03 +00:00 |
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whitequark
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474d46ced8
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back.pysim: implement most operators and add tests.
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2018-12-14 14:21:22 +00:00 |
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whitequark
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d9aaf0114b
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back.pysim: close .vcd/.gtkw files on context manager exit.
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2018-12-14 13:59:03 +00:00 |
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whitequark
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1655b59d1b
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back.pysim: show more legible names for processes in errors.
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2018-12-14 13:50:19 +00:00 |
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whitequark
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625c55a3b8
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back.pysim: throw exceptions back at processes.
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2018-12-14 13:43:25 +00:00 |
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whitequark
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654722ce14
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back.pysim: add gtkw traces even more robustly.
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2018-12-14 13:43:08 +00:00 |
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whitequark
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7d3f7f277a
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back.pysim: accept (and evaluate) generator functions.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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7fc9f98b98
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back.pysim: skip VCD signal population if VCD is not requested.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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3ad79ec690
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back.pysim: allow processes to evaluate expressions.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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151d079f01
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fhdl.ir: oops, we defined DomainError twice.
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2018-12-14 12:59:54 +00:00 |
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whitequark
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dd00b5e2d6
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back.pysim: more general clean-up.
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2018-12-14 12:46:04 +00:00 |
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whitequark
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1b7f8c7950
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back.pysim: general clean-up.
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2018-12-14 12:22:03 +00:00 |
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whitequark
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105113f1d8
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back.pysim: accept any valid assignments from processes.
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2018-12-14 12:18:41 +00:00 |
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whitequark
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240a40c2c2
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back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
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2018-12-14 10:57:13 +00:00 |
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whitequark
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7d91dd56c8
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fhdl.xfrm: implement DomainLowerer.
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2018-12-14 10:56:53 +00:00 |
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whitequark
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b34c1a9ad0
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back.pysim: undriven comb signals should return to reset value.
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2018-12-14 09:12:38 +00:00 |
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whitequark
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b58715c5dc
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ast, back.pysim: allow specifying user-defined decoders for signals.
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2018-12-14 09:02:29 +00:00 |
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whitequark
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bb843cb40c
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back.pysim: fix completely broken codegen for Switch.
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2018-12-14 08:51:36 +00:00 |
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whitequark
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6aefd0c04c
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back.pysim: raise an exception if delta cycles blow a process deadline.
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2018-12-14 08:10:21 +00:00 |
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whitequark
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a10791e160
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back.pysim: if requested, write a gtkw file with a useful preset.
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2018-12-14 08:04:29 +00:00 |
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whitequark
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cb998d891b
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back.pysim: explain how delta cycles work.
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2018-12-14 07:26:26 +00:00 |
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whitequark
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e4d08d2855
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back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
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2018-12-14 05:17:43 +00:00 |
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whitequark
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3bb7a87e0f
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back.pysim: implement "sync processes", like migen.sim generators.
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2018-12-14 05:13:58 +00:00 |
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whitequark
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d791b77cc8
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back.pysim: allow suspending processes until a tick in a domain.
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2018-12-14 04:33:06 +00:00 |
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whitequark
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3e59d857e1
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back.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 03:05:57 +00:00 |
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whitequark
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55e729f68a
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setup: add missing import.
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2018-12-14 02:32:37 +00:00 |
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whitequark
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b09f4b10ee
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back.pysim: collect handlers before running (-5% runtime).
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2018-12-13 18:34:44 +00:00 |
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whitequark
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a7ebc02bdd
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back.pysim: allow multiple registered handlers per signal.
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2018-12-13 18:28:11 +00:00 |
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whitequark
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6a4004ef8d
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back.pysim: fix handling of process termination.
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2018-12-13 18:17:58 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
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fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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ac498414ab
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back.verilog: remove debug code.
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2018-12-13 13:42:54 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
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bb04c9e0da
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fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
|
859c2dbcf0
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back.rtlil: never give subfragment cells names starting with $.
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2018-12-13 11:30:16 +00:00 |
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whitequark
|
b150f1915d
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fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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