whitequark
ed7e07c6c1
hdl.ast: implement Initial.
...
This is the last remaining part for first-class formal support.
2019-08-15 02:53:07 +00:00
whitequark
40abaef858
hdl.xfrm: sample cache should be per-fragment.
2019-08-15 02:45:31 +00:00
whitequark
fa0fa056ba
hdl.xfrm: CEInserter→EnableInserter.
...
Fixes #166 .
2019-08-12 13:39:26 +00:00
whitequark
fdb0c5a6bc
hdl.ir: call back from Fragment.prepare if a clock domain is missing.
...
See #57 .
2019-08-03 14:54:20 +00:00
whitequark
94e13effad
hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
...
Fixes #148 .
2019-08-03 13:07:06 +00:00
whitequark
995e4adb8c
hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
...
Fixes #154 .
2019-07-31 05:20:05 +00:00
whitequark
00c5209a47
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.
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This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff .
2019-07-09 19:26:47 +00:00
whitequark
a7fbff94d8
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
...
Fixes #125 .
2019-07-08 10:26:49 +00:00
whitequark
ec7fcd3697
hdl.xfrm: don't overwrite source locations on ClockDomain signals.
...
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
2019-07-08 09:58:12 +00:00
whitequark
8c9fdf907f
hdl.{dsl,mem,xfrm}: inject appropriate source locations.
...
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.
On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
2019-07-08 09:58:12 +00:00
whitequark
dac6275493
hdl.ast: use keyword-only arguments as appropriate.
...
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
2019-07-08 09:58:12 +00:00
whitequark
82903e493a
back.rtlil: emit \src attributes for processes via Switch and Assign.
...
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
2019-07-03 16:27:54 +00:00
whitequark
48d4ee4031
hdl.ir, back.rtlil: allow specifying attributes on instances.
...
Fixes #107 .
2019-06-28 04:14:38 +00:00
whitequark
ad1a40c934
hdl.ast: implement values with custom lowering.
2019-06-11 07:01:44 +00:00
whitequark
51c03ca391
hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
2019-06-04 10:26:01 +00:00
whitequark
585514e6ed
hdl.ir: rework named port handling for Instances.
...
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.
While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
2019-04-22 07:46:47 +00:00
whitequark
44711b7d08
hdl.ir: detect elaboratables that are created but not used.
...
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3 .
2019-04-21 08:52:57 +00:00
whitequark
dda8f34d39
hdl.xfrm: handle classes that inherit from Record.
2019-04-18 17:06:33 +00:00
whitequark
0a2a7025a6
hdl.xfrm: allow using FragmentTransformer on any elaboratable.
...
Fixes #29 .
2019-04-10 00:23:11 +00:00
whitequark
c5d67b0461
hdl.xfrm: mark internal registers used in lowering Sample().
2019-01-19 07:27:32 +00:00
whitequark
b50b47d984
hdl.ast: give Assert and Assume their own src_loc.
...
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
2019-01-19 00:08:51 +00:00
whitequark
fa8e876356
hdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 05:23:06 +00:00
whitequark
8c96675580
hdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 04:31:27 +00:00
whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
William D. Jones
77728c2dea
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
2019-01-15 22:52:45 +00:00
whitequark
b534e92dd5
hdl.ir: allow explicitly requesting flattening.
2019-01-14 17:04:23 +00:00
whitequark
011bf2258e
hdl: make ClockSignal and ResetSignal usable on LHS.
...
Fixes #8 .
2019-01-14 15:38:16 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
98f554aa08
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
...
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
2018-12-24 02:17:28 +00:00
whitequark
1c7c75a254
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
2018-12-24 02:02:59 +00:00
whitequark
621dddebfd
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
2018-12-22 22:19:14 +00:00
whitequark
ae0cb48fbb
hdl.xfrm: implement LHSGroupAnalyzer.
2018-12-22 06:58:24 +00:00
whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
0f2c7e7161
compat: import genlib.record from Migen.
2018-12-18 20:04:22 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
7341d0d7ef
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
2018-12-18 16:13:29 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
