whitequark
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474d46ced8
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back.pysim: implement most operators and add tests.
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2018-12-14 14:21:22 +00:00 |
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whitequark
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7d91dd56c8
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fhdl.xfrm: implement DomainLowerer.
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2018-12-14 10:56:53 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
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fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
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b150f1915d
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fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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c5087edfa5
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fhdl.cd: add tests.
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2018-12-13 09:19:16 +00:00 |
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whitequark
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9bee90f1bd
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fhdl.xfrm: implement DomainRenamer.
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2018-12-13 08:57:14 +00:00 |
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whitequark
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8963ab5d9f
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fhdl.xfrm: add test for ControlInserter with subfragments.
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2018-12-13 08:45:10 +00:00 |
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whitequark
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19aa404628
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fhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 08:39:02 +00:00 |
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whitequark
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b1a89ef5fd
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fhdl.ir: add tests for port propagation.
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2018-12-13 08:09:39 +00:00 |
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whitequark
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a797e27573
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fhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 07:33:59 +00:00 |
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whitequark
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e0a81edf4d
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fhdl.dsl: add tests for submodules.
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2018-12-13 07:24:28 +00:00 |
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whitequark
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932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
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f70ae3bac5
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fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 06:06:51 +00:00 |
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whitequark
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f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
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dc486ad8b9
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fhdl.ast: add tests for most logic.
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2018-12-13 02:06:55 +00:00 |
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