whitequark
ac13a5b3c9
sim._pyrtl: reject very large values.
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A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.
This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.
Fixes #588 .
2021-12-11 13:00:46 +00:00
whitequark
599615ee3a
hdl.ir: reject elaboratables that elaborate to themselves.
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Fixes #592 .
2021-12-11 12:40:05 +00:00
whitequark
90777a65c8
build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*.
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These have been mistakenly omitted from commit 909a3b8b
2021-12-11 12:40:05 +00:00
Irides
b1eba5fd82
vendor.xilinx: support setting options on synth_design
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Closes #606 .
2021-12-11 12:09:09 +00:00
whitequark
fd7d01ef10
back.rtlil,cli: allow suppressing generation of src attributes.
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Fixes #572 .
2021-12-11 11:38:40 +00:00
whitequark
66295fa388
sim.pysim: refuse to write VCD files with whitespace in signal names.
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Closes #595 .
2021-12-11 11:12:25 +00:00
whitequark
b452e0e871
hdl.ast: support division and modulo with negative divisor.
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Fixes #621 .
This commit bumps the Yosys version requirement to >=0.10.
2021-12-11 10:25:48 +00:00
whitequark
25573c5eff
back.rtlil: extend unsigned operand of binop if another is signed.
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Fixes #580 .
2021-12-11 10:25:48 +00:00
whitequark
44b8bd29af
hdl.ast: warn on bare integer value used in Cat()/Repl().
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Fixes #639 .
2021-12-11 08:18:33 +00:00
whitequark
de7c9acb19
_utils: don't crash trying to flatten() strings.
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Fixes #614 .
2021-12-11 07:39:35 +00:00
whitequark
909a3b8be7
Rename nMigen to Amaranth HDL.
2021-12-10 10:34:13 +00:00
