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  • 27d3dfc453 back.rtlil: fix swapped operands in sync assign. whitequark 2018-12-13 04:34:22 +0000
  • 6c7f98e964 back.rtlil: explain logic for CD reset insertion. whitequark 2018-12-13 03:51:00 +0000
  • 2c67a620ee back.rtlil: explicitly set the top module. whitequark 2018-12-13 03:50:04 +0000
  • 4df5c5de65 fhdl.ir: explain how port enumeration works. whitequark 2018-12-13 03:30:39 +0000
  • f86ec1e7ef back.rtlil: explain how RTLIL conversion works. whitequark 2018-12-13 03:22:01 +0000
  • bfd0011aee fhdl.ir: make sure clocks and resets of used CDs appear as inputs. whitequark 2018-12-13 02:43:22 +0000
  • a17a9e355d back.rtlil: give clocks and resets nicer names. whitequark 2018-12-13 02:43:02 +0000
  • 22c76e5f90 compat.fhdl.module: implement finalization. whitequark 2018-12-13 02:36:15 +0000
  • b42620e490 back.rtlil: match shape of $mux ports A/B/Y. whitequark 2018-12-13 02:35:46 +0000
  • 17767642be tracer: add support for Python 3.7. whitequark 2018-12-13 02:20:00 +0000
  • f0f4c0ce61 fhdl.ast: bits_sign→shape. whitequark 2018-12-13 02:06:49 +0000
  • dc486ad8b9 fhdl.ast: add tests for most logic. whitequark 2018-12-13 02:04:44 +0000
  • e45e7f1608 Measure test coverage. whitequark 2018-12-13 02:04:23 +0000
  • b4dab74b2e compat.fhdl.{module,structure}: import/wrap Migen code (WIP). whitequark 2018-12-12 15:44:54 +0000
  • 356852a570 compat.fhdl.bitcontainer: import/wrap Migen code. whitequark 2018-12-12 14:11:19 +0000
  • 1d4d00aac6 fhdl.ast.Signal: implement .like(). whitequark 2018-12-12 14:43:03 +0000
  • ad9b45adcd fhdl.ir: fix port threading code. whitequark 2018-12-12 13:00:50 +0000
  • 0fac1f8d0f fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. whitequark 2018-12-12 12:38:24 +0000
  • 00f0b950f6 fhdl.ast.Signal: fix typo. whitequark 2018-12-12 12:37:30 +0000
  • aab01d9e59 fhdl.ast.Signal: implement attrs field. whitequark 2018-12-12 11:02:13 +0000
  • c05c189ece genlib.cdc.MultiReg: self.regs should be a private field. whitequark 2018-12-12 10:52:32 +0000
  • 4eadc1629a fhdl.ast.Signal: implement width derivation from min/max. whitequark 2018-12-12 10:43:09 +0000
  • bc60631d68 genlib.cdc.MultiReg: pull in from Migen. whitequark 2018-12-12 10:12:35 +0000
  • 263d577323 fhdl.ast.Signal: implement reset_less signals. whitequark 2018-12-12 10:11:16 +0000
  • 1d46ffb591 fhdl.ast.Signal: assign an internal name if tracer fails. whitequark 2018-12-12 10:08:56 +0000
  • 6d5878a0ee fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom. whitequark 2018-12-12 10:00:00 +0000
  • 851ed06769 ClockDomain.{rst→reset}, for consistency with ResetInserter. whitequark 2018-12-12 09:49:02 +0000
  • 4d3258013d Initial commit. whitequark 2018-12-11 20:50:56 +0000