amaranth/nmigen/hdl
2019-01-14 15:38:16 +00:00
..
__init__.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
ast.py hdl: make ClockSignal and ResetSignal usable on LHS. 2019-01-14 15:38:16 +00:00
cd.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
dsl.py hdl.dsl: cases wider than switch test value are unreachable. 2019-01-13 08:51:49 +00:00
ir.py hdl.ir: add an API for retrieving generated values, like FSM signal. 2018-12-26 12:35:35 +00:00
mem.py hdl.mem: add DummyPort, for testing and verification. 2019-01-01 03:08:10 +00:00
rec.py hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00
xfrm.py hdl: make ClockSignal and ResetSignal usable on LHS. 2019-01-14 15:38:16 +00:00