whitequark
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011bf2258e
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hdl: make ClockSignal and ResetSignal usable on LHS.
Fixes #8.
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2019-01-14 15:38:16 +00:00 |
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whitequark
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664b4bcb3a
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hdl.dsl: cases wider than switch test value are unreachable.
In 3083c1d6 they were erroneously fixed via truncation.
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2019-01-13 08:51:49 +00:00 |
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whitequark
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3083c1d6dd
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hdl.dsl: accept (but warn on) cases wider than switch test value.
Fixes #13.
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2019-01-13 08:46:28 +00:00 |
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whitequark
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a2b04d71d0
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hdl.ast: allow slicing [n:n] into n-bit value.
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2019-01-02 18:14:57 +00:00 |
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William D. Jones
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f77dc40256
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hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
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2019-01-02 11:17:39 +00:00 |
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William D. Jones
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2412650f56
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hdl.dsl: Support Assert and Assume where an Assign can occur.
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2019-01-02 11:17:39 +00:00 |
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William D. Jones
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e6517a33c7
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hdl.ast: Add Assert and Assign statements.
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2019-01-02 11:17:39 +00:00 |
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whitequark
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ea7e19ed5c
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hdl.ast: experimentally add Value._as_const.
Useful for writing e.g. decoders that accept Cat, etc as argument.
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2019-01-01 09:50:39 +00:00 |
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whitequark
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3c07d8d52c
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hdl.rec: include record name in error message.
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2019-01-01 03:39:12 +00:00 |
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whitequark
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031a9e2616
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hdl.rec: use a helpful error on unknown field reference.
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2019-01-01 03:35:34 +00:00 |
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whitequark
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d78e6c155b
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hdl.mem: add DummyPort, for testing and verification.
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2019-01-01 03:08:10 +00:00 |
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whitequark
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39eb2e8fa7
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lib.cdc: fix tests to actually run.
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2018-12-29 15:02:44 +00:00 |
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whitequark
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92a96e1644
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hdl.rec: add basic record support.
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2018-12-28 13:22:10 +00:00 |
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whitequark
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d66bbb0df8
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tracer: factor out get_src_loc().
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2018-12-28 01:31:24 +00:00 |
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whitequark
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470d66934f
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hdl.dsl: add support for fsm.ongoing().
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2018-12-27 16:19:01 +00:00 |
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whitequark
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de50ccec90
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hdl.mem: add missing __all__.
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2018-12-27 16:19:01 +00:00 |
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whitequark
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35a44f017f
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hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
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2018-12-26 12:42:43 +00:00 |
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whitequark
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934546e633
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hdl.dsl: provide generated values for FSMs.
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2018-12-26 12:39:05 +00:00 |
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whitequark
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040811c2e5
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hdl.ir: add an API for retrieving generated values, like FSM signal.
This is useful for tests.
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2018-12-26 12:35:35 +00:00 |
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whitequark
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597d778cf6
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examples: add an FSM usage example (UART receiver).
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2018-12-26 10:10:27 +00:00 |
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whitequark
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72039b6072
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hdl.dsl: add signal decoder to FSM state signal.
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2018-12-26 09:45:12 +00:00 |
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whitequark
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54e3195dcb
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hdl.dsl: implement FSM.
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2018-12-26 08:55:04 +00:00 |
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whitequark
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f05bd2a137
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hdl.mem: allow omitting memory simulation logic.
Trying to transform very large arrays is slow.
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2018-12-24 11:53:59 +00:00 |
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whitequark
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98f554aa08
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hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
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2018-12-24 02:17:28 +00:00 |
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whitequark
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1c7c75a254
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hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
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2018-12-24 02:02:59 +00:00 |
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whitequark
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621dddebfd
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hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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2018-12-22 22:19:14 +00:00 |
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whitequark
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68dae9f50e
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hdl.ir: flatten hierarchy based on memory accesses, too.
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2018-12-22 21:43:46 +00:00 |
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whitequark
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fd89d2fc9d
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hdl.ir: factor out _merge_subfragment. NFC.
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2018-12-22 19:04:49 +00:00 |
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whitequark
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ae0cb48fbb
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hdl.xfrm: implement LHSGroupAnalyzer.
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2018-12-22 06:58:24 +00:00 |
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whitequark
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98a9744be4
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hdl.xfrm: Abstract*Transformer→*Visitor
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2018-12-22 06:03:39 +00:00 |
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whitequark
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8730895d8c
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hdl.mem: allow changing init value after creating memory.
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2018-12-22 01:09:03 +00:00 |
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whitequark
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f6772759c8
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hdl.ir: fix port propagation between siblings, in the other direction.
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2018-12-22 00:31:31 +00:00 |
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whitequark
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a4183eba69
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hdl.mem: use more informative signal naming for ports.
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2018-12-21 23:55:02 +00:00 |
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whitequark
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913339c04a
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hdl.ir: fix port propagation between siblings.
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2018-12-21 23:53:18 +00:00 |
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whitequark
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fc7da1be2d
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hdl.ir: do not flatten instances or collect ports from their statements.
This results in absurd behavior for memories.
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2018-12-21 13:52:18 +00:00 |
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whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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af7db882c0
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hdl.mem: use different naming for array signals.
It looks like [] is confusing gtkwave somehow.
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2018-12-21 12:26:49 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
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a061bfaa6c
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hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
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b0bd7bfaca
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hdl.ir: correctly handle named output and inout ports.
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2018-12-21 04:03:03 +00:00 |
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whitequark
|
6d9a6b5d84
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hdl.mem: implement memories.
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2018-12-21 01:53:32 +00:00 |
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whitequark
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f7fec804ec
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ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
|
0f2c7e7161
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compat: import genlib.record from Migen.
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2018-12-18 20:04:22 +00:00 |
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whitequark
|
dbbcc49a71
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hdl.ast: Cat.{operands→parts}
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2018-12-18 19:15:50 +00:00 |
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whitequark
|
7341d0d7ef
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hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
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2018-12-18 16:13:29 +00:00 |
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whitequark
|
c7f9386eab
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fhdl.ir: add black-box fragments, fragment parameters, and Instance.
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2018-12-17 22:55:39 +00:00 |
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whitequark
|
8d1639a5a8
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hdl, back: add and use SignalSet/SignalDict.
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2018-12-17 17:21:29 +00:00 |
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whitequark
|
8c4de99c0d
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hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
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2018-12-17 17:21:29 +00:00 |
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whitequark
|
850674637a
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back.rtlil: implement Array.
|
2018-12-17 01:15:23 +00:00 |
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