In commit 9faa1d37, the RTLIL backend was changed to ignore modules
without ports completely, since Yosys would recognize empty modules
as black boxes without explicit `write_verilog -noblackbox` and break
the design. That change had many flaws:
* It removed instances without ports, which are used in e.g. SoC
FPGAs to instantiate a dummy CPU.
* It removed fragments without ports, which can appear in e.g. SoC
FPGAs in case the fabric is not connected to any I/O ports.
* Finally, it was just conceptually unjustified.
This commit changes the logic to actually check for empty fragments,
and instead of removing them, it adds a dummy wire inside. It would
be possible to use the Yosys-specific (*noblackbox*) attribute.
However, it would be necessary to strip it for most targets right
away, and also the wire doubles as documentation.
Fixes#441.
07a3685da8