whitequark 1c091e67a4 lib.fifo: remove SyncFIFO.replace. ... This obscure functionality was likely only ever used in old MiSoC code, and doesn't justify the added complexity. It was also not provided (and could not be reasonably provided) in SyncFIFOBuffered, which made its utility extremely marginal.		2019-09-12 19:16:57 +00:00
..
compat	lib.fifo: remove SyncFIFO.replace.	2019-09-12 19:16:57 +00:00
__init__.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_build_dsl.py	build.dsl: allow both str and int resource attributes.	2019-08-30 08:35:52 +00:00
test_build_res.py	build.dsl: add conn argument to Connector.	2019-08-18 19:56:25 +00:00
test_compat.py	compat.fhdl.module: CompatModule should be elaboratable.	2019-06-04 11:11:31 +00:00
test_examples.py	test.test_examples: Convert pathlib-specific class to string.	2019-08-20 00:54:10 +00:00
test_hdl_ast.py	hdl.ast: warn if reset value is truncated.	2019-09-10 07:26:34 +00:00
test_hdl_cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
test_hdl_dsl.py	hdl.dsl: add Default(), an alias for Case() with no arguments.	2019-09-08 12:24:18 +00:00
test_hdl_ir.py	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
test_hdl_mem.py	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
test_hdl_rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
test_hdl_xfrm.py	hdl.xfrm: lower resets in DomainLowerer as well.	2019-08-19 21:44:30 +00:00
test_lib_cdc.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_lib_coding.py	formal→asserts	2019-08-19 20:23:24 +00:00
test_lib_fifo.py	lib.fifo: remove SyncFIFO.replace.	2019-09-12 19:16:57 +00:00
test_lib_io.py	Clean up imports.	2019-06-04 08:18:50 +00:00
test_sim.py	back.pysim: implement sim.add_clock(if_exists=True).	2019-08-23 08:53:48 +00:00
tools.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00