| .. |
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_toolchain
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_yosys→_toolchain.yosys
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2020-07-02 18:26:08 +00:00 |
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back
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back.rtlil: lower maximum accepted wire size.
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2020-07-22 14:43:44 +00:00 |
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build
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vendor.intel: double-quote Tcl values rather than brace-quoting.
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2020-05-21 09:48:42 +00:00 |
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compat
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nmigen.lib.scheduler: add RoundRobin.
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2020-07-28 21:02:01 +00:00 |
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hdl
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hdl.ast: don't inherit Shape from NamedTuple.
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2020-07-07 05:17:03 +00:00 |
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lib
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nmigen.lib.scheduler: add RoundRobin.
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2020-07-28 21:02:01 +00:00 |
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sim
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sim._pycoro: avoid spurious wakeups.
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2020-07-22 14:32:45 +00:00 |
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test
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nmigen.lib.scheduler: add RoundRobin.
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2020-07-28 21:02:01 +00:00 |
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vendor
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vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter.
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2020-07-23 16:38:28 +00:00 |
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__init__.py
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Gracefully handle missing dependencies.
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2020-07-01 07:00:02 +00:00 |
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_unused.py
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_unused: extract must-use logic from hdl.ir.
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2020-02-01 01:35:05 +00:00 |
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_utils.py
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hdl.ir: allow disabling UnusedElaboratable warning in file scope.
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2019-10-26 06:17:14 +00:00 |
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asserts.py
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hdl.ast,back.rtlil: implement Cover.
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2019-09-03 01:32:24 +00:00 |
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cli.py
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back.cxxrtl: new backend.
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2020-06-11 16:19:40 +00:00 |
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rpc.py
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rpc: add public Records as module ports.
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2019-09-30 18:28:21 +00:00 |
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tracer.py
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tracer: fix get_var_name() to work on toplevel attributes.
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2020-05-17 19:51:58 +00:00 |
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utils.py
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{,_}tools→{,_}utils
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2019-10-13 18:53:38 +00:00 |
