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compat
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compat: suppress deprecation warnings that are internal or during test.
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2019-01-26 15:43:00 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.dsl: allow both str and int resource attributes.
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2019-08-30 08:35:52 +00:00 |
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test_build_res.py
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build.dsl: add conn argument to Connector.
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2019-08-18 19:56:25 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_examples.py
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test.test_examples: Convert pathlib-specific class to string.
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2019-08-20 00:54:10 +00:00 |
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test_hdl_ast.py
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hdl.ast: warn if reset value is truncated.
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2019-09-10 07:26:34 +00:00 |
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test_hdl_cd.py
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hdl.cd: add negedge clock domains.
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2019-08-31 22:05:48 +00:00 |
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test_hdl_dsl.py
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hdl.dsl: add Default(), an alias for Case() with no arguments.
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2019-09-08 12:24:18 +00:00 |
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test_hdl_ir.py
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build.plat, hdl.ir: coordinate missing domain creation.
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2019-08-19 22:52:01 +00:00 |
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test_hdl_mem.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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test_hdl_rec.py
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hdl.rec: respect modifications to signals in Record.like().
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2019-07-08 10:59:15 +00:00 |
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test_hdl_xfrm.py
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hdl.xfrm: lower resets in DomainLowerer as well.
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2019-08-19 21:44:30 +00:00 |
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test_lib_cdc.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_coding.py
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formal→asserts
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2019-08-19 20:23:24 +00:00 |
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test_lib_fifo.py
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hdl.mem,lib,examples: use Signal.range().
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2019-09-08 12:19:13 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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back.pysim: implement sim.add_clock(if_exists=True).
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2019-08-23 08:53:48 +00:00 |
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tools.py
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_toolchain,build.plat,vendor.*: add required_tools list and checks.
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2019-08-31 00:05:47 +00:00 |
