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amaranth/nmigen/hdl
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whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
2019-06-28 04:37:08 +00:00
..
__init__.py Clean up imports. 2019-06-04 08:18:50 +00:00
ast.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
cd.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
dsl.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
ir.py hdl.ir, back.rtlil: allow specifying attributes on instances. 2019-06-28 04:14:38 +00:00
mem.py hdl.mem: coerce memory init values to integers. 2019-06-11 03:38:44 +00:00
rec.py hdl.rec: unbreak hasattr(rec, ...). 2019-06-03 07:43:31 +00:00
xfrm.py hdl.ir, back.rtlil: allow specifying attributes on instances. 2019-06-28 04:14:38 +00:00