whitequark 307de722cb back.verilog: remove undriven check. ... This check no longer finds bugs and is prone to false positives. Instead, we should do integration tests on the entire stack, from fragments to Verilog. Fixes #23.		2019-01-08 22:43:09 +00:00
..
back	back.verilog: remove undriven check.	2019-01-08 22:43:09 +00:00
compat	compat.genlib.coding: fix import.	2018-12-26 14:30:01 +00:00
hdl	hdl.ast: allow slicing [n:n] into n-bit value.	2019-01-02 18:14:57 +00:00
lib	lib.coding: fix tests to actually run, and fix code to fix tests.	2018-12-27 21:45:55 +00:00
test	hdl.dsl: Support Assert and Assume where an Assign can occur.	2019-01-02 11:17:39 +00:00
__init__.py	hdl.dsl: Support Assert and Assume where an Assign can occur.	2019-01-02 11:17:39 +00:00
cli.py	cli: generate: guess file type from extension.	2018-12-23 07:13:17 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	tracer: factor out get_src_loc().	2018-12-28 01:31:24 +00:00