whitequark 307de722cb back.verilog: remove undriven check. ... This check no longer finds bugs and is prone to false positives. Instead, we should do integration tests on the entire stack, from fragments to Verilog. Fixes #23.		2019-01-08 22:43:09 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	Give the top level scope a name to fix VCD hierarchy.	2019-01-06 00:10:37 +00:00
rtlil.py	back.rtlil: translate empty slices correctly.	2019-01-02 18:14:29 +00:00
verilog.py	back.verilog: remove undriven check.	2019-01-08 22:43:09 +00:00