307de722cb
This check no longer finds bugs and is prone to false positives. Instead, we should do integration tests on the entire stack, from fragments to Verilog. Fixes #23.
37 lines
707 B
Python
37 lines
707 B
Python
import os
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import subprocess
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from . import rtlil
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__all__ = ["convert"]
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class YosysError(Exception):
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pass
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def convert(*args, **kwargs):
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il_text = rtlil.convert(*args, **kwargs)
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popen = subprocess.Popen([os.getenv("YOSYS", "yosys"), "-q", "-"],
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stdin=subprocess.PIPE,
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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encoding="utf-8")
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verilog_text, error = popen.communicate("""
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# Convert nMigen's RTLIL to readable Verilog.
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read_ilang <<rtlil
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{}
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rtlil
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proc_init
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proc_arst
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proc_dff
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proc_clean
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memory_collect
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write_verilog -norename
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""".format(il_text))
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if popen.returncode:
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raise YosysError(error.strip())
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else:
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return verilog_text
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