whitequark 3e2ecdf2fb build.res,vendor: place clock constraint on port, not net, if possible. ... For most toolchains, these are functionally identical, although ports tend to work a bit better, being the common case. For Vivado, though, it is necessary to place them on the port because its timing analyzer considers input buffer delay. Fixes #301.		2020-02-06 23:37:15 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
lattice_ecp5.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
lattice_ice40.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
lattice_machxo2.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
xilinx_7series.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
xilinx_spartan_3_6.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
xilinx_ultrascale.py	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00