whitequark 37b81309d3 back.rtlil: always initialize the entire memory. ... This avoids reading 'x from the memory in simulation. In general, FPGA memories can only be initialized in block granularity, and zero-initializing is cheap, so this is not a significant issue with resource consumption.		2018-12-22 05:27:42 +00:00
..
back	back.rtlil: always initialize the entire memory.	2018-12-22 05:27:42 +00:00
compat	compat: use nicer names for next_value/next_value_ce signals.	2018-12-22 02:05:49 +00:00
hdl	hdl.mem: allow changing init value after creating memory.	2018-12-22 01:09:03 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.ir: fix port propagation between siblings, in the other direction.	2018-12-22 00:31:31 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00