whitequark 37b81309d3 back.rtlil: always initialize the entire memory. ... This avoids reading 'x from the memory in simulation. In general, FPGA memories can only be initialized in block granularity, and zero-initializing is cheap, so this is not a significant issue with resource consumption.		2018-12-22 05:27:42 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: handle out of bounds ArrayProxy indexes.	2018-12-21 12:32:08 +00:00
rtlil.py	back.rtlil: always initialize the entire memory.	2018-12-22 05:27:42 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00