awygle 4601dd0a69 Correctly handle resets in AsyncFIFO. ... This commit improves handling of resets in AsyncFIFO in two ways: * First, resets no longer violate Gray counter CDC invariants. * Second, write domain reset now empties the entire FIFO.		2020-03-14 23:26:07 +00:00
..
back	back.pysim: fix RHS codegen for Cat() and Repl(..., 0).	2020-02-19 01:21:00 +00:00
build	build.res,vendor: place clock constraint on port, not net, if possible.	2020-02-06 23:37:15 +00:00
compat	nmigen.compat.genlib.cdc: add PulseSynchronizer.	2020-02-16 07:01:44 +00:00
hdl	Correctly handle resets in AsyncFIFO.	2020-03-14 23:26:07 +00:00
lib	Correctly handle resets in AsyncFIFO.	2020-03-14 23:26:07 +00:00
test	Correctly handle resets in AsyncFIFO.	2020-03-14 23:26:07 +00:00
vendor	vendor: fix a few issues in commit 2f8669ca.	2020-03-12 20:29:17 +00:00
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	cli: update use of deprecated code.	2020-02-12 14:42:24 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00