whitequark 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns. ... Fixes #207.		2019-09-16 19:22:12 +00:00
..
__init__.py	hdl.xfrm: CEInserter→EnableInserter.	2019-08-12 13:39:26 +00:00
ast.py	hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.	2019-09-16 19:22:12 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.	2019-09-16 19:22:12 +00:00
ir.py	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
mem.py	hdl.mem: use keyword-only arguments as appropriate.	2019-09-12 20:03:48 +00:00
rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
xfrm.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00