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_toolchain
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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back
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back.{verilog,rtlil}: fix commit d83c4a1b.
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2021-12-14 10:47:04 +00:00 |
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build
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build.dsl: check type of resource number.
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2021-12-11 13:37:15 +00:00 |
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compat
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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hdl
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hdl.ir: reject elaboratables that elaborate to themselves.
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2021-12-11 12:40:05 +00:00 |
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lib
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lib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC.
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2021-12-13 09:53:57 +00:00 |
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sim
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sim.pysim: use "bench" as a top level root for testbench signals.
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2021-12-16 15:46:05 +00:00 |
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test
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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vendor
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docs: cover amaranth.vendor.
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2021-12-13 09:17:50 +00:00 |
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__init__.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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_unused.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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_utils.py
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_utils: don't crash trying to flatten() strings.
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2021-12-11 07:39:35 +00:00 |
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asserts.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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cli.py
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back.rtlil,cli: allow suppressing generation of src attributes.
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2021-12-11 11:38:40 +00:00 |
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rpc.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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tracer.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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utils.py
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
