whitequark 585514e6ed hdl.ir: rework named port handling for Instances. ... The main purpose of this rework is cleanup, to avoid specifying the direction of input ports in an implicit, ad-hoc way using the named ports and ports dictionaries. While working on this I realized that output ports can be connected to anything that is valid on LHS, so this is now supported too.		2019-04-22 07:46:47 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: support async reset.	2019-01-26 18:07:43 +00:00
rtlil.py	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
verilog.py	back.verilog: better error message if Yosys is not found.	2019-01-13 08:10:23 +00:00