585514e6ed
The main purpose of this rework is cleanup, to avoid specifying the direction of input ports in an implicit, ad-hoc way using the named ports and ports dictionaries. While working on this I realized that output ports can be connected to anything that is valid on LHS, so this is now supported too.
862 lines
30 KiB
Python
862 lines
30 KiB
Python
import io
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import textwrap
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from collections import defaultdict, OrderedDict
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from contextlib import contextmanager
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from ..tools import bits_for
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from ..hdl import ast, rec, ir, mem, xfrm
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__all__ = ["convert"]
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class _Namer:
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def __init__(self):
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super().__init__()
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self._index = 0
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self._names = set()
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def _make_name(self, name, local):
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if name is None:
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self._index += 1
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name = "${}".format(self._index)
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elif not local and name[0] not in "\\$":
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name = "\\{}".format(name)
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while name in self._names:
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self._index += 1
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name = "{}${}".format(name, self._index)
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self._names.add(name)
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return name
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class _Bufferer:
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_escape_map = str.maketrans({
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"\"": "\\\"",
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"\\": "\\\\",
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"\t": "\\t",
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"\r": "\\r",
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"\n": "\\n",
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})
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def __init__(self):
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super().__init__()
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self._buffer = io.StringIO()
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def __str__(self):
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return self._buffer.getvalue()
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def _append(self, fmt, *args, **kwargs):
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self._buffer.write(fmt.format(*args, **kwargs))
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def attribute(self, name, value, indent=0):
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if isinstance(value, str):
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self._append("{}attribute \\{} \"{}\"\n",
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" " * indent, name, value.translate(self._escape_map))
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else:
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self._append("{}attribute \\{} {}\n",
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" " * indent, name, int(value))
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def _src(self, src):
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if src:
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self.attribute("src", src)
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class _Builder(_Namer, _Bufferer):
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def module(self, name=None, attrs={}):
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name = self._make_name(name, local=False)
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return _ModuleBuilder(self, name, attrs)
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class _ModuleBuilder(_Namer, _Bufferer):
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def __init__(self, rtlil, name, attrs):
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super().__init__()
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self.rtlil = rtlil
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self.name = name
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self.attrs = {"generator": "nMigen"}
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self.attrs.update(attrs)
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def __enter__(self):
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for name, value in self.attrs.items():
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self.attribute(name, value, indent=0)
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self._append("module {}\n", self.name)
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return self
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def __exit__(self, *args):
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self._append("end\n")
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self.rtlil._buffer.write(str(self))
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def attribute(self, name, value, indent=1):
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super().attribute(name, value, indent)
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def wire(self, width, port_id=None, port_kind=None, name=None, src=""):
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self._src(src)
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name = self._make_name(name, local=False)
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if port_id is None:
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self._append(" wire width {} {}\n", width, name)
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else:
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assert port_kind in ("input", "output", "inout")
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self._append(" wire width {} {} {} {}\n", width, port_kind, port_id, name)
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return name
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def connect(self, lhs, rhs):
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self._append(" connect {} {}\n", lhs, rhs)
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def memory(self, width, size, name=None, src=""):
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self._src(src)
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name = self._make_name(name, local=False)
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self._append(" memory width {} size {} {}\n", width, size, name)
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return name
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def cell(self, kind, name=None, params={}, ports={}, src=""):
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self._src(src)
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name = self._make_name(name, local=False)
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self._append(" cell {} {}\n", kind, name)
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for param, value in params.items():
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if isinstance(value, str):
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self._append(" parameter \\{} \"{}\"\n",
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param, value.translate(self._escape_map))
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elif isinstance(value, int):
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self._append(" parameter \\{} {:d}\n",
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param, value)
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elif isinstance(value, ast.Const):
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self._append(" parameter \\{} {}'{:b}\n",
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param, len(value), value.value)
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else:
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assert False
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for port, wire in ports.items():
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self._append(" connect {} {}\n", port, wire)
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self._append(" end\n")
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return name
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def process(self, name=None, src=""):
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name = self._make_name(name, local=True)
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return _ProcessBuilder(self, name, src)
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class _ProcessBuilder(_Bufferer):
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def __init__(self, rtlil, name, src):
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super().__init__()
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self.rtlil = rtlil
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self.name = name
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self.src = src
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def __enter__(self):
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self._src(self.src)
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self._append(" process {}\n", self.name)
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return self
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def __exit__(self, *args):
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self._append(" end\n")
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self.rtlil._buffer.write(str(self))
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def case(self):
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return _CaseBuilder(self, indent=2)
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def sync(self, kind, cond=None):
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return _SyncBuilder(self, kind, cond)
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class _CaseBuilder:
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def __init__(self, rtlil, indent):
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self.rtlil = rtlil
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self.indent = indent
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def __enter__(self):
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return self
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def __exit__(self, *args):
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pass
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def assign(self, lhs, rhs):
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self.rtlil._append("{}assign {} {}\n", " " * self.indent, lhs, rhs)
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def switch(self, cond):
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return _SwitchBuilder(self.rtlil, cond, self.indent)
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class _SwitchBuilder:
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def __init__(self, rtlil, cond, indent):
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self.rtlil = rtlil
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self.cond = cond
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self.indent = indent
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def __enter__(self):
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self.rtlil._append("{}switch {}\n", " " * self.indent, self.cond)
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return self
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def __exit__(self, *args):
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self.rtlil._append("{}end\n", " " * self.indent)
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def case(self, value=None):
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if value is None:
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self.rtlil._append("{}case\n", " " * (self.indent + 1))
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else:
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self.rtlil._append("{}case {}'{}\n", " " * (self.indent + 1),
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len(value), value)
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return _CaseBuilder(self.rtlil, self.indent + 2)
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class _SyncBuilder:
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def __init__(self, rtlil, kind, cond):
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self.rtlil = rtlil
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self.kind = kind
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self.cond = cond
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def __enter__(self):
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if self.cond is None:
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self.rtlil._append(" sync {}\n", self.kind)
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else:
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self.rtlil._append(" sync {} {}\n", self.kind, self.cond)
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return self
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def __exit__(self, *args):
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pass
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def update(self, lhs, rhs):
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self.rtlil._append(" update {} {}\n", lhs, rhs)
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def src(src_loc):
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file, line = src_loc
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return "{}:{}".format(file, line)
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class LegalizeValue(Exception):
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def __init__(self, value, branches):
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self.value = value
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self.branches = list(branches)
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class _ValueCompilerState:
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def __init__(self, rtlil):
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self.rtlil = rtlil
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self.wires = ast.SignalDict()
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self.driven = ast.SignalDict()
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self.ports = ast.SignalDict()
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self.anys = ast.ValueDict()
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self.expansions = ast.ValueDict()
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def add_driven(self, signal, sync):
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self.driven[signal] = sync
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def add_port(self, signal, kind):
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assert kind in ("i", "o", "io")
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if kind == "i":
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kind = "input"
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elif kind == "o":
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kind = "output"
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elif kind == "io":
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kind = "inout"
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self.ports[signal] = (len(self.ports), kind)
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def resolve(self, signal, prefix=None):
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if signal in self.wires:
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return self.wires[signal]
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if signal in self.ports:
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port_id, port_kind = self.ports[signal]
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else:
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port_id = port_kind = None
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if prefix is not None:
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wire_name = "{}_{}".format(prefix, signal.name)
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else:
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wire_name = signal.name
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for attr_name, attr_signal in signal.attrs.items():
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self.rtlil.attribute(attr_name, attr_signal)
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wire_curr = self.rtlil.wire(width=signal.nbits, name=wire_name,
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port_id=port_id, port_kind=port_kind,
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src=src(signal.src_loc))
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if signal in self.driven:
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wire_next = self.rtlil.wire(width=signal.nbits, name="$next" + wire_curr,
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src=src(signal.src_loc))
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else:
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wire_next = None
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self.wires[signal] = (wire_curr, wire_next)
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return wire_curr, wire_next
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def resolve_curr(self, signal, prefix=None):
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wire_curr, wire_next = self.resolve(signal, prefix)
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return wire_curr
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def expand(self, value):
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if not self.expansions:
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return value
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return self.expansions.get(value, value)
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@contextmanager
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def expand_to(self, value, expansion):
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try:
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assert value not in self.expansions
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self.expansions[value] = expansion
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yield
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finally:
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del self.expansions[value]
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class _ValueCompiler(xfrm.ValueVisitor):
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def __init__(self, state):
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self.s = state
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def on_unknown(self, value):
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if value is None:
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return None
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else:
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super().on_unknown(value)
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Sample(self, value):
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raise NotImplementedError # :nocov:
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def on_Record(self, value):
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return self(ast.Cat(value.fields.values()))
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def on_Cat(self, value):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.parts])))
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def _prepare_value_for_Slice(self, value):
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raise NotImplementedError # :nocov:
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def on_Slice(self, value):
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if value.start == 0 and value.end == len(value.value):
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return self(value.value)
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sigspec = self._prepare_value_for_Slice(value.value)
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if value.start == value.end:
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return "{}"
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elif value.start + 1 == value.end:
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return "{} [{}]".format(sigspec, value.start)
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else:
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return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
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def on_ArrayProxy(self, value):
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index = self.s.expand(value.index)
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if isinstance(index, ast.Const):
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if index.value < len(value.elems):
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elem = value.elems[index.value]
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else:
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elem = value.elems[-1]
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return self.match_shape(elem, *value.shape())
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else:
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raise LegalizeValue(value.index, range(len(value.elems)))
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class _RHSValueCompiler(_ValueCompiler):
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operator_map = {
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(1, "~"): "$not",
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(1, "-"): "$neg",
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(1, "b"): "$reduce_bool",
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(2, "+"): "$add",
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(2, "-"): "$sub",
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(2, "*"): "$mul",
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(2, "/"): "$div",
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(2, "%"): "$mod",
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(2, "**"): "$pow",
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(2, "<<"): "$sshl",
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(2, ">>"): "$sshr",
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(2, "&"): "$and",
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(2, "^"): "$xor",
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(2, "|"): "$or",
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(2, "=="): "$eq",
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(2, "!="): "$ne",
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(2, "<"): "$lt",
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(2, "<="): "$le",
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(2, ">"): "$gt",
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(2, ">="): "$ge",
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(3, "m"): "$mux",
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}
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def on_value(self, value):
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return super().on_value(self.s.expand(value))
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def on_Const(self, value):
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if isinstance(value.value, str):
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return "{}'{}".format(value.nbits, value.value)
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else:
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value_twos_compl = value.value & ((1 << value.nbits) - 1)
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return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
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def on_AnyConst(self, value):
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if value in self.s.anys:
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return self.s.anys[value]
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res_bits, res_sign = value.shape()
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell("$anyconst", ports={
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"\\Y": res,
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}, params={
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"WIDTH": res_bits,
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}, src=src(value.src_loc))
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self.s.anys[value] = res
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return res
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def on_AnySeq(self, value):
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if value in self.s.anys:
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return self.s.anys[value]
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res_bits, res_sign = value.shape()
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell("$anyseq", ports={
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"\\Y": res,
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}, params={
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"WIDTH": res_bits,
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}, src=src(value.src_loc))
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self.s.anys[value] = res
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return res
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def on_Signal(self, value):
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wire_curr, wire_next = self.s.resolve(value)
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return wire_curr
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def on_Operator_unary(self, value):
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arg, = value.operands
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arg_bits, arg_sign = arg.shape()
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res_bits, res_sign = value.shape()
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell(self.operator_map[(1, value.op)], ports={
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"\\A": self(arg),
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"\\Y": res,
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}, params={
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"A_SIGNED": arg_sign,
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"A_WIDTH": arg_bits,
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"Y_WIDTH": res_bits,
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}, src=src(value.src_loc))
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return res
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def match_shape(self, value, new_bits, new_sign):
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if isinstance(value, ast.Const):
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return self(ast.Const(value.value, (new_bits, new_sign)))
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value_bits, value_sign = value.shape()
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if new_bits <= value_bits:
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return self(ast.Slice(value, 0, new_bits))
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res = self.s.rtlil.wire(width=new_bits)
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self.s.rtlil.cell("$pos", ports={
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"\\A": self(value),
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"\\Y": res,
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}, params={
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"A_SIGNED": value_sign,
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"A_WIDTH": value_bits,
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"Y_WIDTH": new_bits,
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}, src=src(value.src_loc))
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return res
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def on_Operator_binary(self, value):
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lhs, rhs = value.operands
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lhs_bits, lhs_sign = lhs.shape()
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rhs_bits, rhs_sign = rhs.shape()
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if lhs_sign == rhs_sign:
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lhs_wire = self(lhs)
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rhs_wire = self(rhs)
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else:
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lhs_sign = rhs_sign = True
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lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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res_bits, res_sign = value.shape()
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell(self.operator_map[(2, value.op)], ports={
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"\\A": lhs_wire,
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"\\B": rhs_wire,
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"\\Y": res,
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}, params={
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"A_SIGNED": lhs_sign,
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"A_WIDTH": lhs_bits,
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"B_SIGNED": rhs_sign,
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"B_WIDTH": rhs_bits,
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"Y_WIDTH": res_bits,
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}, src=src(value.src_loc))
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return res
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def on_Operator_mux(self, value):
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sel, val1, val0 = value.operands
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val1_bits, val1_sign = val1.shape()
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val0_bits, val0_sign = val0.shape()
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res_bits, res_sign = value.shape()
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val1_bits = val0_bits = res_bits = max(val1_bits, val0_bits, res_bits)
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val1_wire = self.match_shape(val1, val1_bits, val1_sign)
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val0_wire = self.match_shape(val0, val0_bits, val0_sign)
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell("$mux", ports={
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"\\A": val0_wire,
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"\\B": val1_wire,
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"\\S": self(sel),
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"\\Y": res,
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}, params={
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"WIDTH": res_bits
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}, src=src(value.src_loc))
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return res
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def on_Operator(self, value):
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if len(value.operands) == 1:
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return self.on_Operator_unary(value)
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elif len(value.operands) == 2:
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return self.on_Operator_binary(value)
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elif len(value.operands) == 3:
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assert value.op == "m"
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return self.on_Operator_mux(value)
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else:
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raise TypeError # :nocov:
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def _prepare_value_for_Slice(self, value):
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if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
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sigspec = self(value)
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else:
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sigspec = self.s.rtlil.wire(len(value))
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self.s.rtlil.connect(sigspec, self(value))
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return sigspec
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def on_Part(self, value):
|
|
lhs, rhs = value.value, value.offset
|
|
lhs_bits, lhs_sign = lhs.shape()
|
|
rhs_bits, rhs_sign = rhs.shape()
|
|
res_bits, res_sign = value.shape()
|
|
res = self.s.rtlil.wire(width=res_bits)
|
|
# Note: Verilog's x[o+:w] construct produces a $shiftx cell, not a $shift cell.
|
|
# However, Migen's semantics defines the out-of-range bits to be zero, so it is correct
|
|
# to use a $shift cell here instead, even though it produces less idiomatic Verilog.
|
|
self.s.rtlil.cell("$shift", ports={
|
|
"\\A": self(lhs),
|
|
"\\B": self(rhs),
|
|
"\\Y": res,
|
|
}, params={
|
|
"A_SIGNED": lhs_sign,
|
|
"A_WIDTH": lhs_bits,
|
|
"B_SIGNED": rhs_sign,
|
|
"B_WIDTH": rhs_bits,
|
|
"Y_WIDTH": res_bits,
|
|
}, src=src(value.src_loc))
|
|
return res
|
|
|
|
def on_Repl(self, value):
|
|
return "{{ {} }}".format(" ".join(self(value.value) for _ in range(value.count)))
|
|
|
|
|
|
class _LHSValueCompiler(_ValueCompiler):
|
|
def on_Const(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_AnyConst(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_AnySeq(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_Operator(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def match_shape(self, value, new_bits, new_sign):
|
|
assert value.shape() == (new_bits, new_sign)
|
|
return self(value)
|
|
|
|
def on_Signal(self, value):
|
|
wire_curr, wire_next = self.s.resolve(value)
|
|
if wire_next is None:
|
|
raise ValueError("No LHS wire for non-driven signal {}".format(repr(value)))
|
|
return wire_next
|
|
|
|
def _prepare_value_for_Slice(self, value):
|
|
assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, rec.Record))
|
|
return self(value)
|
|
|
|
def on_Part(self, value):
|
|
offset = self.s.expand(value.offset)
|
|
if isinstance(offset, ast.Const):
|
|
return self(ast.Slice(value.value, offset.value, offset.value + value.width))
|
|
else:
|
|
raise LegalizeValue(value.offset, range((1 << len(value.offset))))
|
|
|
|
def on_Repl(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
|
|
class _StatementCompiler(xfrm.StatementVisitor):
|
|
def __init__(self, state, rhs_compiler, lhs_compiler):
|
|
self.state = state
|
|
self.rhs_compiler = rhs_compiler
|
|
self.lhs_compiler = lhs_compiler
|
|
|
|
self._case = None
|
|
self._test_cache = {}
|
|
self._has_rhs = False
|
|
|
|
@contextmanager
|
|
def case(self, switch, value):
|
|
try:
|
|
old_case = self._case
|
|
with switch.case(value) as self._case:
|
|
yield
|
|
finally:
|
|
self._case = old_case
|
|
|
|
def _check_rhs(self, value):
|
|
if self._has_rhs or next(iter(value._rhs_signals()), None) is not None:
|
|
self._has_rhs = True
|
|
|
|
def on_Assign(self, stmt):
|
|
self._check_rhs(stmt.rhs)
|
|
|
|
lhs_bits, lhs_sign = stmt.lhs.shape()
|
|
rhs_bits, rhs_sign = stmt.rhs.shape()
|
|
if lhs_bits == rhs_bits:
|
|
rhs_sigspec = self.rhs_compiler(stmt.rhs)
|
|
else:
|
|
# In RTLIL, LHS and RHS of assignment must have exactly same width.
|
|
rhs_sigspec = self.rhs_compiler.match_shape(
|
|
stmt.rhs, lhs_bits, lhs_sign)
|
|
self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
|
|
|
|
def on_Assert(self, stmt):
|
|
self(stmt._check.eq(stmt.test))
|
|
self(stmt._en.eq(1))
|
|
|
|
en_wire = self.rhs_compiler(stmt._en)
|
|
check_wire = self.rhs_compiler(stmt._check)
|
|
self.state.rtlil.cell("$assert", ports={
|
|
"\\A": check_wire,
|
|
"\\EN": en_wire,
|
|
}, src=src(stmt.src_loc))
|
|
|
|
def on_Assume(self, stmt):
|
|
self(stmt._check.eq(stmt.test))
|
|
self(stmt._en.eq(1))
|
|
|
|
en_wire = self.rhs_compiler(stmt._en)
|
|
check_wire = self.rhs_compiler(stmt._check)
|
|
self.state.rtlil.cell("$assume", ports={
|
|
"\\A": check_wire,
|
|
"\\EN": en_wire,
|
|
}, src=src(stmt.src_loc))
|
|
|
|
def on_Switch(self, stmt):
|
|
self._check_rhs(stmt.test)
|
|
|
|
if stmt not in self._test_cache:
|
|
self._test_cache[stmt] = self.rhs_compiler(stmt.test)
|
|
test_sigspec = self._test_cache[stmt]
|
|
|
|
with self._case.switch(test_sigspec) as switch:
|
|
for value, stmts in stmt.cases.items():
|
|
with self.case(switch, value):
|
|
self.on_statements(stmts)
|
|
|
|
def on_statement(self, stmt):
|
|
try:
|
|
super().on_statement(stmt)
|
|
except LegalizeValue as legalize:
|
|
with self._case.switch(self.rhs_compiler(legalize.value)) as switch:
|
|
bits, sign = legalize.value.shape()
|
|
tests = ["{:0{}b}".format(v, bits) for v in legalize.branches]
|
|
tests[-1] = "-" * bits
|
|
for branch, test in zip(legalize.branches, tests):
|
|
with self.case(switch, test):
|
|
branch_value = ast.Const(branch, (bits, sign))
|
|
with self.state.expand_to(legalize.value, branch_value):
|
|
super().on_statement(stmt)
|
|
|
|
def on_statements(self, stmts):
|
|
for stmt in stmts:
|
|
self.on_statement(stmt)
|
|
|
|
|
|
def convert_fragment(builder, fragment, hierarchy):
|
|
if isinstance(fragment, ir.Instance):
|
|
port_map = OrderedDict()
|
|
for port_name, (value, dir) in fragment.named_ports.items():
|
|
port_map["\\{}".format(port_name)] = value
|
|
|
|
if fragment.type[0] == "$":
|
|
return fragment.type, port_map
|
|
else:
|
|
return "\\{}".format(fragment.type), port_map
|
|
|
|
module_name = hierarchy[-1] or "anonymous"
|
|
module_attrs = {}
|
|
if len(hierarchy) == 1:
|
|
module_attrs["top"] = 1
|
|
module_attrs["nmigen.hierarchy"] = ".".join(name or "anonymous" for name in hierarchy)
|
|
|
|
with builder.module(module_name, attrs=module_attrs) as module:
|
|
compiler_state = _ValueCompilerState(module)
|
|
rhs_compiler = _RHSValueCompiler(compiler_state)
|
|
lhs_compiler = _LHSValueCompiler(compiler_state)
|
|
stmt_compiler = _StatementCompiler(compiler_state, rhs_compiler, lhs_compiler)
|
|
|
|
verilog_trigger = None
|
|
verilog_trigger_sync_emitted = False
|
|
|
|
# Register all signals driven in the current fragment. This must be done first, as it
|
|
# affects further codegen; e.g. whether $next\sig signals will be generated and used.
|
|
for domain, signal in fragment.iter_drivers():
|
|
compiler_state.add_driven(signal, sync=domain is not None)
|
|
|
|
# Transform all signals used as ports in the current fragment eagerly and outside of
|
|
# any hierarchy, to make sure they get sensible (non-prefixed) names.
|
|
for signal in fragment.ports:
|
|
compiler_state.add_port(signal, fragment.ports[signal])
|
|
compiler_state.resolve_curr(signal)
|
|
|
|
# Transform all clocks clocks and resets eagerly and outside of any hierarchy, to make
|
|
# sure they get sensible (non-prefixed) names. This does not affect semantics.
|
|
for domain, _ in fragment.iter_sync():
|
|
cd = fragment.domains[domain]
|
|
compiler_state.resolve_curr(cd.clk)
|
|
if cd.rst is not None:
|
|
compiler_state.resolve_curr(cd.rst)
|
|
|
|
# Transform all subfragments to their respective cells. Transforming signals connected
|
|
# to their ports into wires eagerly makes sure they get sensible (prefixed with submodule
|
|
# name) names.
|
|
memories = OrderedDict()
|
|
for subfragment, sub_name in fragment.subfragments:
|
|
if not subfragment.ports:
|
|
continue
|
|
|
|
sub_params = OrderedDict()
|
|
if hasattr(subfragment, "parameters"):
|
|
for param_name, param_value in subfragment.parameters.items():
|
|
if isinstance(param_value, mem.Memory):
|
|
memory = param_value
|
|
if memory not in memories:
|
|
memories[memory] = module.memory(width=memory.width, size=memory.depth,
|
|
name=memory.name)
|
|
addr_bits = bits_for(memory.depth)
|
|
data_parts = []
|
|
for addr in range(memory.depth):
|
|
if addr < len(memory.init):
|
|
data = memory.init[addr]
|
|
else:
|
|
data = 0
|
|
data_parts.append("{:0{}b}".format(data, memory.width))
|
|
module.cell("$meminit", ports={
|
|
"\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
|
|
"\\DATA": "{}'".format(memory.width * memory.depth) +
|
|
"".join(reversed(data_parts)),
|
|
}, params={
|
|
"MEMID": memories[memory],
|
|
"ABITS": addr_bits,
|
|
"WIDTH": memory.width,
|
|
"WORDS": memory.depth,
|
|
"PRIORITY": 0,
|
|
})
|
|
|
|
param_value = memories[memory]
|
|
|
|
sub_params[param_name] = param_value
|
|
|
|
sub_type, sub_port_map = \
|
|
convert_fragment(builder, subfragment, hierarchy=hierarchy + (sub_name,))
|
|
|
|
sub_ports = OrderedDict()
|
|
for port, value in sub_port_map.items():
|
|
for signal in value._rhs_signals():
|
|
compiler_state.resolve_curr(signal, prefix=sub_name)
|
|
sub_ports[port] = rhs_compiler(value)
|
|
|
|
module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params)
|
|
|
|
# If we emit all of our combinatorial logic into a single RTLIL process, Verilog
|
|
# simulators will break horribly, because Yosys write_verilog transforms RTLIL processes
|
|
# into always @* blocks with blocking assignment, and that does not create delta cycles.
|
|
#
|
|
# Therefore, we translate the fragment as many times as there are independent groups
|
|
# of signals (a group is a transitive closure of signals that appear together on LHS),
|
|
# splitting them into many RTLIL (and thus Verilog) processes.
|
|
lhs_grouper = xfrm.LHSGroupAnalyzer()
|
|
lhs_grouper.on_statements(fragment.statements)
|
|
|
|
for group, group_signals in lhs_grouper.groups().items():
|
|
lhs_group_filter = xfrm.LHSGroupFilter(group_signals)
|
|
|
|
with module.process(name="$group_{}".format(group)) as process:
|
|
with process.case() as case:
|
|
# For every signal in comb domain, assign $next\sig to the reset value.
|
|
# For every signal in sync domains, assign $next\sig to the current
|
|
# value (\sig).
|
|
for domain, signal in fragment.iter_drivers():
|
|
if signal not in group_signals:
|
|
continue
|
|
if domain is None:
|
|
prev_value = ast.Const(signal.reset, signal.nbits)
|
|
else:
|
|
prev_value = signal
|
|
case.assign(lhs_compiler(signal), rhs_compiler(prev_value))
|
|
|
|
# Convert statements into decision trees.
|
|
stmt_compiler._case = case
|
|
stmt_compiler._has_rhs = False
|
|
stmt_compiler(lhs_group_filter(fragment.statements))
|
|
|
|
# Verilog `always @*` blocks will not run if `*` does not match anything, i.e.
|
|
# if the implicit sensitivity list is empty. We check this while translating,
|
|
# by looking for any signals on RHS. If there aren't any, we add some logic
|
|
# whose only purpose is to trigger Verilog simulators when it converts
|
|
# through RTLIL and to Verilog, by populating the sensitivity list.
|
|
if not stmt_compiler._has_rhs:
|
|
if verilog_trigger is None:
|
|
verilog_trigger = \
|
|
module.wire(1, name="$verilog_initial_trigger")
|
|
case.assign(verilog_trigger, verilog_trigger)
|
|
|
|
# For every signal in the sync domain, assign \sig's initial value (which will
|
|
# end up as the \init reg attribute) to the reset value.
|
|
with process.sync("init") as sync:
|
|
for domain, signal in fragment.iter_sync():
|
|
if signal not in group_signals:
|
|
continue
|
|
wire_curr, wire_next = compiler_state.resolve(signal)
|
|
sync.update(wire_curr, rhs_compiler(ast.Const(signal.reset, signal.nbits)))
|
|
|
|
# The Verilog simulator trigger needs to change at time 0, so if we haven't
|
|
# yet done that in some process, do it.
|
|
if verilog_trigger and not verilog_trigger_sync_emitted:
|
|
sync.update(verilog_trigger, "1'0")
|
|
verilog_trigger_sync_emitted = True
|
|
|
|
# For every signal in every domain, assign \sig to $next\sig. The sensitivity list,
|
|
# however, differs between domains: for comb domains, it is `always`, for sync
|
|
# domains with sync reset, it is `posedge clk`, for sync domains with async reset
|
|
# it is `posedge clk or posedge rst`.
|
|
for domain, signals in fragment.drivers.items():
|
|
signals = signals & group_signals
|
|
if not signals:
|
|
continue
|
|
|
|
triggers = []
|
|
if domain is None:
|
|
triggers.append(("always",))
|
|
else:
|
|
cd = fragment.domains[domain]
|
|
triggers.append(("posedge", compiler_state.resolve_curr(cd.clk)))
|
|
if cd.async_reset:
|
|
triggers.append(("posedge", compiler_state.resolve_curr(cd.rst)))
|
|
|
|
for trigger in triggers:
|
|
with process.sync(*trigger) as sync:
|
|
for signal in signals:
|
|
wire_curr, wire_next = compiler_state.resolve(signal)
|
|
sync.update(wire_curr, wire_next)
|
|
|
|
# Finally, collect the names we've given to our ports in RTLIL, and correlate these with
|
|
# the signals represented by these ports. If we are a submodule, this will be necessary
|
|
# to create a cell for us in the parent module.
|
|
port_map = OrderedDict()
|
|
for signal in fragment.ports:
|
|
port_map[compiler_state.resolve_curr(signal)] = signal
|
|
|
|
return module.name, port_map
|
|
|
|
|
|
def convert(fragment, name="top", **kwargs):
|
|
fragment = ir.Fragment.get(fragment, platform=None).prepare(**kwargs)
|
|
builder = _Builder()
|
|
convert_fragment(builder, fragment, hierarchy=(name,))
|
|
return str(builder)
|