whitequark 585514e6ed hdl.ir: rework named port handling for Instances. ... The main purpose of this rework is cleanup, to avoid specifying the direction of input ports in an implicit, ad-hoc way using the named ports and ports dictionaries. While working on this I realized that output ports can be connected to anything that is valid on LHS, so this is now supported too.		2019-04-22 07:46:47 +00:00
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back	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
compat	lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.	2019-04-15 16:27:23 +00:00
hdl	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
lib	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
__init__.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	formal: extract from toplevel module.	2019-01-17 01:43:07 +00:00
tools.py	compat: suppress deprecation warnings that are internal or during test.	2019-01-26 15:43:00 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00