| back | back.pysim: check for a clock being added twice. | 2019-06-11 03:54:22 +00:00 | 
		
			
			
			
			
				| build | build.plat: dedent overrides. | 2019-06-16 12:40:52 +00:00 | 
		
			
			
			
			
				| compat | compat.fhdl.structure: fix Case().makedefault(). | 2019-06-13 03:56:57 +00:00 | 
		
			
			
			
			
				| hdl | hdl.ast: tighten assertion in Switch(). | 2019-06-13 03:56:57 +00:00 | 
		
			
			
			
			
				| lib | lib.cdc: fix typo. | 2019-06-09 10:24:01 +00:00 | 
		
			
			
			
			
				| __init__.py | Clean up imports. | 2019-06-04 08:18:50 +00:00 | 
		
			
			
			
			
				| _version.py | Add versioneer. | 2019-05-26 11:20:13 +00:00 | 
		
			
			
			
			
				| cli.py | hdl.ir: rename .get_fragment() to .elaborate(). | 2019-01-26 02:31:12 +00:00 | 
		
			
			
			
			
				| formal.py | Clean up imports. | 2019-06-04 08:18:50 +00:00 | 
		
			
			
			
			
				| tracer.py | tracer: factor out get_var_name(default=). | 2019-03-03 18:21:22 +00:00 |