amaranth/nmigen
2019-05-20 16:34:31 +00:00
..
back back.rtlil: assign undriven signals to their reset value. 2019-05-13 08:33:55 +00:00
build build.dsl: style. NFC. 2019-04-24 15:02:30 +00:00
compat Add import so that Tristate.elaborate builds 2019-05-20 16:34:31 +00:00
hdl hdl.ir: when adding sync domain to a design, also add it to ports. 2019-05-15 06:44:50 +00:00
lib lib.io: add a name argument to the Pin constructor. 2019-04-24 22:02:20 +00:00
test hdl.ir: when adding sync domain to a design, also add it to ports. 2019-05-15 06:44:50 +00:00
__init__.py hdl.ir: detect elaboratables that are created but not used. 2019-04-21 08:52:57 +00:00
cli.py hdl.ir: rename .get_fragment() to .elaborate(). 2019-01-26 02:31:12 +00:00
formal.py formal: extract from toplevel module. 2019-01-17 01:43:07 +00:00
tools.py hdl: make all public Value classes other than Record final. 2019-05-12 05:40:17 +00:00
tracer.py tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00