whitequark c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. ... Otherwise we end up in a situation where the examples don't have clk and rst as ports, which is not nice. Fixes #67.		2019-05-15 06:44:50 +00:00
..
__init__.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
ast.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
ir.py	hdl.ir: when adding sync domain to a design, also add it to ports.	2019-05-15 06:44:50 +00:00
mem.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
rec.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
xfrm.py	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00