whitequark 6ee80408bb back.verilog: do not rename internal signals. ... _0_ is not really any better than \$13, and the latter at least has continuity between nMigen, RTLIL and Verilog.		2018-12-22 00:53:40 +00:00
..
back	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00
compat	compat: fix confusing naming for memory port address signal.	2018-12-22 00:53:05 +00:00
hdl	hdl.ir: fix port propagation between siblings, in the other direction.	2018-12-22 00:31:31 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.ir: fix port propagation between siblings, in the other direction.	2018-12-22 00:31:31 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00