whitequark 6fae06aea9 build.{dsl,plat,res}: allow dir="oe". ... Although a dir="oe" pin is generally equivalent to dir="io" pin with the i* signal(s) disconnected, they are not equivalent, because some pins may not be able to support input buffers at all, either because there are no input buffers, or because the input buffers are consumed by some other resource. E.g. this can happen on iCE40 when the input buffer is consumed by a PLL.		2019-06-03 04:42:55 +00:00
..
back	back.rtlil: allow specifying platform for convert().	2019-05-26 17:10:56 +00:00
build	build.{dsl,plat,res}: allow dir="oe".	2019-06-03 04:42:55 +00:00
compat	Add import so that Tristate.elaborate builds	2019-05-20 16:34:31 +00:00
hdl	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
lib	lib.io: allow dir="oe".	2019-06-03 04:28:53 +00:00
test	build.{dsl,plat,res}: allow dir="oe".	2019-06-03 04:42:55 +00:00
vendor	build.{dsl,plat,res}: allow dir="oe".	2019-06-03 04:42:55 +00:00
__init__.py	Add versioneer.	2019-05-26 11:20:13 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	formal: extract from toplevel module.	2019-01-17 01:43:07 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00