whitequark 6fae06aea9 build.{dsl,plat,res}: allow dir="oe". ... Although a dir="oe" pin is generally equivalent to dir="io" pin with the i* signal(s) disconnected, they are not equivalent, because some pins may not be able to support input buffers at all, either because there are no input buffers, or because the input buffers are consumed by some other resource. E.g. this can happen on iCE40 when the input buffer is consumed by a PLL.		2019-06-03 04:42:55 +00:00
..
compat	compat: suppress deprecation warnings that are internal or during test.	2019-01-26 15:43:00 +00:00
__init__.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_build_dsl.py	build.{dsl,plat,res}: allow dir="oe".	2019-06-03 04:42:55 +00:00
test_build_res.py	build.{dsl,plat,res}: allow dir="oe".	2019-06-03 04:42:55 +00:00
test_hdl_ast.py	hdl.ast: improve tests for exceptional conditions.	2019-04-21 07:20:00 +00:00
test_hdl_cd.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_dsl.py	hdl.dsl: allow adding submodules with computed name, like with domains.	2019-06-03 02:22:55 +00:00
test_hdl_ir.py	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
test_hdl_mem.py	hdl.mem: add DummyPort, for testing and verification.	2019-01-01 03:08:10 +00:00
test_hdl_rec.py	hdl.rec: allow providing fields during construction.	2019-05-25 22:06:56 +00:00
test_hdl_xfrm.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_lib_cdc.py	lib.cdc: add ResetSynchronizer.	2019-01-26 18:07:59 +00:00
test_lib_coding.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_lib_fifo.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test_lib_io.py	lib.io: allow dir="oe".	2019-06-03 04:28:53 +00:00
test_sim.py	test_sim: add missing add_process().	2019-03-28 17:50:14 +00:00
tools.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00