whitequark 702e41ba3c vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal. ... In commit 892cff05, `-decimal` was used when writing Verilog for Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *) differently in violation of Verilog LRM. However, it is possible to avoid that workaround by using (* keep="TRUE" *). Do that, and remove `-decimal` to avoid special-casing 32-bit constants. Refs #373.		2020-05-21 08:57:43 +00:00
..
back	back.rtlil: handle signed and large Instance parameters correctly.	2020-05-19 23:33:14 +00:00
build	build.plat: skip clock constraints on unused signals.	2020-05-20 05:35:47 +00:00
compat	Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation	2020-04-02 02:46:44 +00:00
hdl	hdl.ast: add const-shift operations.	2020-05-20 03:18:33 +00:00
lib	lib.cdc: add missing documentation for AsyncFFSynchronizer. NFC.	2020-04-27 02:20:29 +00:00
test	hdl.ast: add const-shift operations.	2020-05-20 03:18:33 +00:00
vendor	vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal.	2020-05-21 08:57:43 +00:00
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	cli: update use of deprecated code.	2020-02-12 14:42:24 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix get_var_name() to work on toplevel attributes.	2020-05-17 19:51:58 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00