whitequark 702e41ba3c vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal. ... In commit 892cff05, `-decimal` was used when writing Verilog for Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *) differently in violation of Verilog LRM. However, it is possible to avoid that workaround by using (* keep="TRUE" *). Do that, and remove `-decimal` to avoid special-casing 32-bit constants. Refs #373.		2020-05-21 08:57:43 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.	2020-05-20 04:58:03 +00:00
lattice_ecp5.py	plat, vendor: systematically escape net and file names in Tcl.	2020-05-02 10:41:18 +00:00
lattice_ice40.py	plat, vendor: systematically escape net and file names in Tcl.	2020-05-02 10:41:18 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: generate binary bitstreams.	2020-05-08 04:42:21 +00:00
xilinx_7series.py	vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal.	2020-05-21 08:57:43 +00:00
xilinx_spartan_3_6.py	vendor: fix typo async_ff_sync	2020-03-15 11:34:52 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal.	2020-05-21 08:57:43 +00:00