schwigi 8184efd612 vendor.intel: fix output enable width for XDR=0 case. ... Fixes #297.		2020-01-09 10:09:35 +00:00
..
back	back.rtlil: do not consider unreachable array elements when legalizing.	2020-01-01 15:26:05 +00:00
build	build.run: fix indentation.	2020-01-07 12:57:49 +00:00
compat	back.pysim: redesign the simulator.	2019-11-28 21:05:34 +00:00
hdl	hdl.mem: fix src_loc_at in ReadPort, WritePort.	2019-12-15 11:46:26 +00:00
lib	lib.io: use keyword-only arguments in Pin().	2019-10-16 19:50:04 +00:00
test	hdl.ast: Fix width for unary minus operator on signed argument.	2019-12-04 06:55:35 +00:00
vendor	vendor.intel: fix output enable width for XDR=0 case.	2020-01-09 10:09:35 +00:00
__init__.py	Explicitly restrict prelude imports.	2019-10-21 10:39:21 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00