whitequark 4d6ad28f59 back.verilog: remove $verilog_initial_trigger after proc_prune. ... $verilog_initial_trigger was introduced to work around Verilog simulation semantics issues with `always @*` statements that only have constants on RHS and in conditions. Unfortunately, it breaks Verilator. Since the combination of proc_prune and proc_clean passes eliminates all such statements, it can be simply removed when both of these passes are available, currently on Yosys master. After Yosys 0.10 is released, we can get rid of $verilog_initial_trigger entirely.		2019-10-28 10:11:41 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
rtlil.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00