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amaranth/tests
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Marcelina Kościelnicka 8c4a15ab92 hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
2023-09-03 03:27:51 +00:00
..
compat Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
__init__.py tests: move out of the main package. 2020-08-27 00:33:31 +00:00
test_build_dsl.py build.dsl: check type of resource number. 2021-12-11 13:37:15 +00:00
test_build_plat.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
test_build_res.py hdl.rec: deprecate in favor of lib.data and lib.wiring. 2023-09-01 04:20:16 +00:00
test_compat.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
test_examples.py tests: move out of the main package. 2020-08-27 00:33:31 +00:00
test_hdl_ast.py Implement RFC 22: Add ValueCastable.shape(). 2023-08-23 10:48:48 +00:00
test_hdl_cd.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
test_hdl_dsl.py hdl.dsl: py3.12+: turn off heuristic warning on ~True and ~False. 2023-06-02 13:45:15 +01:00
test_hdl_ir.py hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 2023-09-03 03:27:51 +00:00
test_hdl_mem.py hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 2023-09-03 03:27:51 +00:00
test_hdl_rec.py hdl.rec: deprecate in favor of lib.data and lib.wiring. 2023-09-01 04:20:16 +00:00
test_hdl_xfrm.py hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 2023-09-03 03:27:51 +00:00
test_lib_cdc.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
test_lib_coding.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
test_lib_crc.py Implement RFC 6: CRC Generator 2023-06-29 02:42:47 +00:00
test_lib_data.py Implement RFC 22: Add ValueCastable.shape(). 2023-08-23 10:48:48 +00:00
test_lib_enum.py lib.enum: allow empty enums. 2023-07-04 10:28:22 +00:00
test_lib_fifo.py hdl.ast: deprecate Sample, Past, Rose, Fell, Stable. 2023-02-28 14:30:04 +00:00
test_lib_io.py hdl.rec: deprecate in favor of lib.data and lib.wiring. 2023-09-01 04:20:16 +00:00
test_lib_scheduler.py Implement RFC 19: Remove amaranth.lib.scheduler 2023-09-01 00:56:12 +00:00
test_lib_wiring.py lib.wiring: ensure flipped(flipped(intf)) is intf. 2023-09-01 05:42:04 +00:00
test_sim.py hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 2023-09-03 03:27:51 +00:00
test_tracer.py tracer: fix STORE_DEREF handling, add EXTENDED_ARG support. 2023-06-01 19:18:43 +01:00
utils.py Drop support for Python 3.7. 2023-06-28 14:50:30 +00:00