whitequark 9749c70730 hdl.ir: lower domains before resolving hierarchy conflicts. ... Otherwise, two subfragments with the same local clock domain would not be able to drive its clock or reset signals. This can be easily hit if using two ResetSynchronizers in one module. Fixes #265.		2019-11-07 08:20:27 +00:00
..
__init__.py	Explicitly restrict prelude imports.	2019-10-21 10:39:21 +00:00
ast.py	hdl.ast: simplify {bit,word}_select with constant offset.	2019-10-26 00:09:53 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
ir.py	hdl.ir: lower domains before resolving hierarchy conflicts.	2019-11-07 08:20:27 +00:00
mem.py	test: use #nmigen: magic comment instead of monkey patch.	2019-10-26 06:37:08 +00:00
rec.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
xfrm.py	test: use #nmigen: magic comment instead of monkey patch.	2019-10-26 06:37:08 +00:00