whitequark 9749c70730 hdl.ir: lower domains before resolving hierarchy conflicts. ... Otherwise, two subfragments with the same local clock domain would not be able to drive its clock or reset signals. This can be easily hit if using two ResetSynchronizers in one module. Fixes #265.		2019-11-07 08:20:27 +00:00
..
back	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00
build	lib.io: use keyword-only arguments in Pin().	2019-10-16 19:50:04 +00:00
compat	compat.fhdl.specials: fix argument parsing compatibility.	2019-10-17 07:54:36 +00:00
hdl	hdl.ir: lower domains before resolving hierarchy conflicts.	2019-11-07 08:20:27 +00:00
lib	lib.io: use keyword-only arguments in Pin().	2019-10-16 19:50:04 +00:00
test	hdl.ir: lower domains before resolving hierarchy conflicts.	2019-11-07 08:20:27 +00:00
vendor	vendor.lattice_ice40: fix commit 88649def.	2019-10-14 15:55:11 +00:00
__init__.py	Explicitly restrict prelude imports.	2019-10-21 10:39:21 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00