whitequark 6d9852506f vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. ... Fixes #438 (again).		2020-08-26 15:45:58 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
lattice_ecp5.py	vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir correctly	2020-08-10 17:52:47 +00:00
lattice_ice40.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: add back as a compatibility shim.	2020-06-21 17:28:01 +00:00
lattice_machxo_2_3l.py	vendor.lattice_machxo_2_3l: add SRAM svf generation	2020-08-24 14:41:14 +00:00
xilinx_7series.py	vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.	2020-08-26 15:45:58 +00:00
xilinx_spartan_3_6.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.	2020-08-26 15:45:58 +00:00