whitequark a1c58633e6 hdl.dsl: make referencing undefined FSM states an error. ... Before this commit, doing something like: with m.FSM(): with m.State("FOO"): m.next = "bAR" with m.State("BAR"): m.next = "FOO" would silently create an empty state `bAR` and get stuck in it until the module is reset. This was done intentionally (in Migen, this code would in fact miscompile), but in retrospect was clearly a bad idea; it turns typos into bugs, while in the rare case that branching to a completely empty state is desired, it is trivial to define one. Fixes #315.		2020-02-06 17:47:46 +00:00
..
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
ast.py	hdl.{ast,dsl}: allow whitespace in bit patterns.	2020-02-04 07:54:54 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.dsl: make referencing undefined FSM states an error.	2020-02-06 17:47:46 +00:00
ir.py	hdl.ir: type check ports.	2020-02-06 17:33:41 +00:00
mem.py	hdl.mem: add synthesis attribute support.	2020-02-06 14:53:16 +00:00
rec.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
xfrm.py	hdl.ast: warn on unused property statements (Assert, Assume, etc).	2020-02-01 02:03:23 +00:00