amaranth/nmigen
whitequark a1c58633e6 hdl.dsl: make referencing undefined FSM states an error.
Before this commit, doing something like:

    with m.FSM():
        with m.State("FOO"):
            m.next = "bAR"
        with m.State("BAR"):
            m.next = "FOO"

would silently create an empty state `bAR` and get stuck in it until
the module is reset. This was done intentionally (in Migen, this code
would in fact miscompile), but in retrospect was clearly a bad idea;
it turns typos into bugs, while in the rare case that branching to
a completely empty state is desired, it is trivial to define one.

Fixes #315.
2020-02-06 17:47:46 +00:00
..
back back.pysim: emit toplevel inputs in VCD files as well. 2020-02-06 17:19:47 +00:00
build build.plat: align pipeline with Fragment.prepare(). 2020-02-01 03:26:04 +00:00
compat _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
hdl hdl.dsl: make referencing undefined FSM states an error. 2020-02-06 17:47:46 +00:00
lib Remove everything deprecated in nmigen 0.1. 2020-01-12 13:59:26 +00:00
test hdl.dsl: make referencing undefined FSM states an error. 2020-02-06 17:47:46 +00:00
vendor vendor.lattice_ecp5: support internal oscillator (OSCG). 2020-01-31 03:18:36 +00:00
__init__.py Remove everything deprecated in nmigen 0.1. 2020-01-12 13:59:26 +00:00
_toolchain.py Refactor build script toolchain lookups. 2019-10-13 13:53:24 +00:00
_unused.py _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
_utils.py hdl.ir: allow disabling UnusedElaboratable warning in file scope. 2019-10-26 06:17:14 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py hdl.ir: rename .get_fragment() to .elaborate(). 2019-01-26 02:31:12 +00:00
rpc.py rpc: add public Records as module ports. 2019-09-30 18:28:21 +00:00
tracer.py tracer: fix typo. 2019-08-19 20:20:18 +00:00
utils.py {,_}tools→{,_}utils 2019-10-13 18:53:38 +00:00