back
hdl.ast: rename Slice.end back to Slice.stop.
2019-10-12 22:40:48 +00:00
build
Refactor build script toolchain lookups.
2019-10-13 13:53:24 +00:00
hdl
hdl.ir: allow ClockSignal and ResetSignal in ports.
2019-10-13 03:39:56 +00:00
test
hdl.ir: allow ClockSignal and ResetSignal in ports.
2019-10-13 03:39:56 +00:00
vendor
Refactor build script toolchain lookups.
2019-10-13 13:53:24 +00:00
__init__.py
Remove nmigen.lib from prelude.
2019-09-06 06:53:06 +00:00
_toolchain.py
Refactor build script toolchain lookups.
2019-10-13 13:53:24 +00:00
asserts.py
hdl.ast,back.rtlil: implement Cover.
2019-09-03 01:32:24 +00:00
cli.py
hdl.ir: rename .get_fragment() to .elaborate().
2019-01-26 02:31:12 +00:00
rpc.py
rpc: add public Records as module ports.
2019-09-30 18:28:21 +00:00
tracer.py
tracer: fix typo.
2019-08-19 20:20:18 +00:00