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compat
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compat: suppress deprecation warnings that are internal or during test.
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2019-01-26 15:43:00 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.{dsl,res,plat}: apply clock constraints to signals, not resources.
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2019-06-05 08:52:30 +00:00 |
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test_build_res.py
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build.res: allow querying frequency of a previously constrained clock.
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2019-06-05 12:51:53 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_hdl_ast.py
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hdl.ast: implement values with custom lowering.
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2019-06-11 07:01:44 +00:00 |
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test_hdl_cd.py
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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test_hdl_dsl.py
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hdl.dsl: allow adding submodules with computed name, like with domains.
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2019-06-03 02:22:55 +00:00 |
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test_hdl_ir.py
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hdl.ir: accept LHS signals like slices as Instance io ports.
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2019-06-03 02:39:14 +00:00 |
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test_hdl_mem.py
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hdl.mem: coerce memory init values to integers.
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2019-06-11 03:38:44 +00:00 |
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test_hdl_rec.py
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hdl.rec: unbreak hasattr(rec, ...).
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2019-06-03 07:43:31 +00:00 |
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test_hdl_xfrm.py
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hdl.ast: implement values with custom lowering.
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2019-06-11 07:01:44 +00:00 |
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test_lib_cdc.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_coding.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_fifo.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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back.pysim: check for a clock being added twice.
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2019-06-11 03:54:22 +00:00 |
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tools.py
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hdl.ir: rename .get_fragment() to .elaborate().
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2019-01-26 02:31:12 +00:00 |
