Marcelina Kościelnicka bdbe8bff27 Unify Xilinx platforms into a single class, support more devices ... This merges existing code, and also adds support for: - Virtex, Virtex E (also known as Spartan 2, Spartan 2E) - Virtex 2, Virtex 2 Pro - Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A DSP support) - Virtex 4 - Virtex 5 - Virtex 6 - ISE synthesis for Series 7 Fixes #552.		2021-09-25 05:04:06 +00:00
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__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	vendor.intel: implement add_settings (QSF) and add_constraints (SDC) overrides.	2020-11-24 20:35:58 +00:00
lattice_ecp5.py	vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts.	2021-04-12 09:48:20 +00:00
lattice_ice40.py	build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.	2020-11-10 05:30:30 +00:00
lattice_machxo2.py	sim: split into base, core, and engines.	2020-08-27 11:52:31 +00:00
lattice_machxo_2_3l.py	vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts.	2021-04-12 09:48:20 +00:00
quicklogic.py	vendor.quicklogic: enable SoC clock configuration	2020-11-13 16:27:15 +00:00
xilinx.py	Unify Xilinx platforms into a single class, support more devices	2021-09-25 05:04:06 +00:00
xilinx_7series.py	Unify Xilinx platforms into a single class, support more devices	2021-09-25 05:04:06 +00:00
xilinx_spartan_3_6.py	Unify Xilinx platforms into a single class, support more devices	2021-09-25 05:04:06 +00:00
xilinx_ultrascale.py	Unify Xilinx platforms into a single class, support more devices	2021-09-25 05:04:06 +00:00