| back | vendor.intel: add Quartus support. | 2019-10-10 00:35:13 +00:00 | 
		
			
			
			
			
				| build | vendor.intel: add Quartus support. | 2019-10-10 00:35:13 +00:00 | 
		
			
			
			
			
				| compat | lib.cdc: MultiReg→FFSynchronizer. | 2019-09-23 14:18:45 +00:00 | 
		
			
			
			
			
				| test | hdl.ast: prohibit signed divisors. | 2019-10-04 07:49:24 +00:00 | 
		
			
			
			
			
				| vendor | xilinx_7series: add grade platform property. | 2019-10-10 16:33:00 +00:00 | 
		
			
			
			
			
				| __init__.py | Remove nmigen.lib from prelude. | 2019-09-06 06:53:06 +00:00 | 
		
			
			
			
			
				| asserts.py | hdl.ast,back.rtlil: implement Cover. | 2019-09-03 01:32:24 +00:00 | 
		
			
			
			
			
				| cli.py | hdl.ir: rename .get_fragment() to .elaborate(). | 2019-01-26 02:31:12 +00:00 | 
		
			
			
			
			
				| rpc.py | rpc: add public Records as module ports. | 2019-09-30 18:28:21 +00:00 | 
		
			
			
			
			
				| tracer.py | tracer: fix typo. | 2019-08-19 20:20:18 +00:00 |