whitequark 3327deae92 vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.		2019-06-03 03:01:56 +00:00
..
fpga	vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.	2019-06-03 03:01:56 +00:00
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
ice40_hx1k_blink_evn.py	build.dsl: require a dict for extras instead of a stringly array.	2019-06-02 23:36:21 +00:00
icestick.py	build.dsl: require a dict for extras instead of a stringly array.	2019-06-02 23:36:21 +00:00
tinyfpga_bx.py	build.dsl: require a dict for extras instead of a stringly array.	2019-06-02 23:36:21 +00:00