whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. ... This is unlikely to work with anything except Slice and Cat, but there's no especially good place to enforce it. (Maybe in Instance?)		2019-06-03 02:39:14 +00:00
..
__init__.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
ast.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	hdl.dsl: allow adding submodules with computed name, like with domains.	2019-06-03 02:22:55 +00:00
ir.py	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
mem.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
rec.py	hdl.rec: allow providing fields during construction.	2019-05-25 22:06:56 +00:00
xfrm.py	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00