whitequark d964ba9cc4 build,vendor: never carry around parts of differential signals. ... When a port component is skipped, it should appear neither in the RTL nor in the constraint file. However, passing around components of differential ports explicitly makes that harder. Fixes #456. Supersedes #457. Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>		2020-07-31 18:41:59 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
lattice_ecp5.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
lattice_ice40.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: add back as a compatibility shim.	2020-06-21 17:28:01 +00:00
lattice_machxo_2_3l.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
xilinx_7series.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
xilinx_spartan_3_6.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
xilinx_ultrascale.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00