whitequark d964ba9cc4 build,vendor: never carry around parts of differential signals. ... When a port component is skipped, it should appear neither in the RTL nor in the constraint file. However, passing around components of differential ports explicitly makes that harder. Fixes #456. Supersedes #457. Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>		2020-07-31 18:41:59 +00:00
..
_toolchain	_yosys→_toolchain.yosys	2020-07-02 18:26:08 +00:00
back	back.rtlil: lower maximum accepted wire size.	2020-07-22 14:43:44 +00:00
build	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
compat	nmigen.lib.scheduler: add RoundRobin.	2020-07-28 21:02:01 +00:00
hdl	hdl.mem: cast reset value for transparent read ports to integer.	2020-07-30 07:05:18 +00:00
lib	nmigen.lib.scheduler: add RoundRobin.	2020-07-28 21:02:01 +00:00
sim	sim._pycoro: avoid spurious wakeups.	2020-07-22 14:32:45 +00:00
test	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
vendor	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
__init__.py	Gracefully handle missing dependencies.	2020-07-01 07:00:02 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	back.cxxrtl: new backend.	2020-06-11 16:19:40 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix get_var_name() to work on toplevel attributes.	2020-05-17 19:51:58 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00