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amaranth/nmigen/test
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whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
2019-06-28 04:37:08 +00:00
..
compat compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
__init__.py hdl.ir: detect elaboratables that are created but not used. 2019-04-21 08:52:57 +00:00
test_build_dsl.py build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
test_build_res.py build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
test_compat.py compat.fhdl.module: CompatModule should be elaboratable. 2019-06-04 11:11:31 +00:00
test_hdl_ast.py hdl.ast: add name_suffix=".." option to Signal.like(). 2019-06-12 22:26:57 +00:00
test_hdl_cd.py hdl.mem: add tests for all error conditions. 2018-12-21 06:07:16 +00:00
test_hdl_dsl.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
test_hdl_ir.py hdl.ir, back.rtlil: allow specifying attributes on instances. 2019-06-28 04:14:38 +00:00
test_hdl_mem.py hdl.mem: coerce memory init values to integers. 2019-06-11 03:38:44 +00:00
test_hdl_rec.py hdl.rec: unbreak hasattr(rec, ...). 2019-06-03 07:43:31 +00:00
test_hdl_xfrm.py hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
test_lib_cdc.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_lib_coding.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_lib_fifo.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_lib_io.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_sim.py back.pysim: check for a clock being added twice. 2019-06-11 03:54:22 +00:00
tools.py hdl.ir: rename .get_fragment() to .elaborate(). 2019-01-26 02:31:12 +00:00