whitequark f70ae3bac5 fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.		2018-12-13 06:06:51 +00:00
..
back	back.verilog: detect undriven public wires using Yosys.	2018-12-13 04:59:48 +00:00
compat	compat.fhdl.module: implement finalization.	2018-12-13 02:36:15 +00:00
fhdl	fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.	2018-12-13 06:06:51 +00:00
genlib	fhdl.ast: bits_sign→shape.	2018-12-13 02:06:58 +00:00
test	fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.	2018-12-13 06:06:51 +00:00
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
tools.py	compat.fhdl.{module,structure}: import/wrap Migen code (WIP).	2018-12-12 15:47:34 +00:00
tracer.py	tracer: add support for Python 3.7.	2018-12-13 02:20:00 +00:00